Simulador de pulsos do TileCal em tempo real utilizando o processador SAPHO e FPGA

Abstract

The Large Hadron Collider (LHC) is the world’s largest particle accelerator, operated by CERN, and investigates the fundamental structure of matter through high-energy proton-proton collisions. In each operation cycle, the detectors record large volumes of data. Between 2026 and 2030, the LHC will remain off for upgrades preceding Phase 2, the High Luminosity LHC (HL-LHC), during which no real data will be acquired. In this context, real-time simulators capable of accurately reproducing detector signals become strategic tools for maintaining research progress, contributing to the development and validation of new methodologies. This work presents the development of a pulse simulator for the Tile Calorimeter (TileCal) of the ATLAS experiment, implemented in Field Programmable Gate Arrays (FPGAs) from code generated by the soft-core SAPHO processor. The aim is to enable, with low latency, the free-running generation of pulses with pile-up effects, allowing tests at the LHC event rate (40 MHz) as if they were real data. The proposed methodology integrates: (i) a multiplicative congruential pseudo-random generator to define event occurrence; (ii) addressing of a precomputed exponential table to produce amplitudes consistent with physical responses; and (iii) pulse modeling using digital filters to emulate pile-up. SAPHO compiles a C subset into Verilog, allocating only the required hardware (fixed- or floating-point), thus facilitating the exploration of different architectures. Four simulators were designed: two with integer processors (separate and combined filtering equations) and two with floating-point processors (a single-core version and another with five parallel processors). The results show significant performance gains, with the number of clocks per sample reduced from 5104 in the integer architecture to 31 in the parallel floating-point version — an improvement of more than two orders of magnitude compared to the first prototype, approaching the practical feasibility in modern FPGAs.