Simulation and testing of the upgraded digital signal processing firmware using high-level synthesis on the real-time trigger path of the ATLAS liquid argon calorimeters

Abstract

This thesis presents the validation and simulation of the upgraded digital signal processing pipeline deployed in the ATLAS Liquid Argon Calorimeter trigger system, with a particular focus on the LATOME firmware. The implementation relies on High-Level Synthesis (HLS) to generate the Input Switch Matrix (ISM) and Output Summing (OSUM) blocks, which are responsible for reorganizing, processing, and aggregating real-time Super Cell data across multiple clock domains. Firmware versions 6.0 through 6.3 were analyzed in depth, with early versions centered on the monitoring path and REMAP validation, and later iterations introducing support for eFEX and jFEX trigger paths. A multilayered simulation strategy was adopted, combining Firmware-Agnostic and FirmwareAware models to enable comprehensive testing from standalone HLS components to fully integrated firmware deployments. Key validation efforts included SOP delay calibration, metastability window identification, and functional verification of clock synchronization logic. The integration of the Mini-FEX diagnostic module provided real-time observability of SOP and CRC errors, both in simulation and during ATLAS system operation. The methodology developed throughout this work offers a reusable and scalable framework for validating future firmware upgrades—such as the gFEX path (v6.4) and the User Code block (v7.x)—and serves as a reference for adopting HLS in other high-throughput, low-latency FPGA-based systems in high-energy physics experiments.